Semiconductor memory device, and method of controlling the same

ABSTRACT

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device having alow power consumption mode.

2. Description of the Related Art

In recent years, the cellular phone has been given not only a functionto have a vocal communication but also a function to transmitcharacter-string data or image data. Moreover, the cellular phone hasbeen expected in the future to become a kind of information terminal(for example, a portable type personal computer) as the internetservices are diversified. Thus, the information volume of data to behandled by the cellular phone has been drastically increasing.Conventionally, the cellular phone has employed as its work memory SRAMshaving a memory capacity of about 4 Mbit. The work memory is a memoryfor retaining the necessary data during the operation of the cellularphone. It is obvious that the memory capacity of the work memory will beshort in the future.

On the other hand, the transmission speed of the cellular phone has beenheightening. The smaller the cellular phone becomes, the smaller thebattery to be mounted becomes. Therefore, the work memory to be employedin the cellular phone is required to have a high speed, low powerconsumption and a large capacity. In the cellular phone serious pricecompetitions, it is necessary to make the costs for parts as low aspossible. Therefore, the work memory has to be at low price.

The conventional SRAMs as employed in the work memory are higher per bitin cost than DRAMs. The production number of SRAMs is smaller than thatof the DRAMs so that it is difficult to lower its price. Moreover, therehave never been developed SRAMs having a large memory capacity (forexample, 64 Mbit).

In this situation, it has been considered to replace the SRAMs by flashmemories and DRAMs in the work memory of the cellular phone.

The flash memory has a power consumption as low as several μW during astandby state but requires several is to several tens μs for writingdata. When the flash memory is employed as the work memory of thecellular phone, therefore, it is difficult to transmit/receive massivedata at high speed. The flash memory performs the write operation at theunit of a sector so that it is not suitable for rewriting bit by bitimage data such as the data of a moving image.

On the contrary, the DRAMs can execute both the read operation and thewrite operation within several tens ns and can process the data of themoving image easily. The power consumption during the standby state ishigher than that of the flash memories. In the present DRAMs, the powerconsumption in the standby state is about 1 mW during a self-refreshmode for retaining written data and about 300 μW during a standby modenot required for retaining written data.

If the power consumption during the standby mode could be reduced tothat of the flash memories, the DRAMs could be employed as the workmemory of the cellular phone, but such circuit technology has never beenproposed.

The power consumption of the DRAMs can be reduced to zero by stoppingthe power supply to the DRAMs. However, since the address terminals, thedata terminals and the like of the DRAMs are connected with theterminals of other electronic parts through the wiring patterns on acircuit board, it is required to drastically change the system of thecellular phone (the pattern change of the circuit board, re-layout andso on) for the termination of the power supply to the DRAMs.

Besides, there has not been proposed a technology which realizes exitfrom the standby mode without the malfunction of an internal circuitafter the power supply is terminated to stop the operation of theinternal circuit during the standby mode.

Where the internal voltage to be used in the internal circuit isgenerated inside of the device, it has to be quickly returned to apredetermined voltage when a release is made from a standby mode (a lowpower consumption mode). However, this technique has never beenproposed.

SUMMARY OF THE INVENTION

An object of the present invention is to enter the device into a lowpower consumption mode and exit the device from a low power consumptionmode with reliability.

Another object of the present invention is to provide a semiconductormemory device capable of drastically reducing current consumption duringstandby mode as compared with the conventional devices and a method ofcontrolling the semiconductor memory device.

Still another object of the present invention is to provide asemiconductor memory device capable of drastically reducing currentconsumption during a standby period as compared with the conventionaldevices and a method of controlling the semiconductor memory device.

Another object of the present invention is to easily enter a device intoa low power consumption mode by a control signal from the exterior.

Another object of the present invention is to prevent the feedthroughcurrent (or leak path) of an internal circuit during a low powerconsumption mode.

Still another object of the present invention is to easily enter thedevice into the low power consumption mode by employing an existingcontrol signal.

Another object of the present invention is to easily enter the deviceinto the low power consumption mode by a command input.

Another object of the present invention is to easily enter the deviceinto the low power consumption mode by a dedicated control signal.

Another object of the invention is to quickly return from the low powerconsumption mode.

According to one aspect of the semiconductor memory device in thepresent invention, an internal voltage generator when activated,generates an internal voltage to be supplied to an internal circuit.When the internal voltage generator is operated, a predetermined amountof electric power is consumed. In response to a control signal from theexterior, an entry circuit inactivates the internal voltage generator.The internal voltage is not to be generated due to the inactivation ofthe internal voltage generator so that the power consumption may bereduced. In response to the control signal from the exterior, therefore,it is possible to easily enter the device into the low power consumptionmode.

According to another aspect of the semiconductor memory device in thepresent invention, in response to the control signal from the exterior,the entry circuit stops the operation of a booster and the generation ofa boost voltage to be supplied to a word line. During the low powerconsumption mode the booster steadily consuming the electric power stopsso that the power consumption is drastically reduced.

According to another aspect of the semiconductor memory device in thepresent invention, in response to the control signal from the exterior,the entry circuit stops the operation of a substrate voltage generatorto stop the generation of a substrate voltage to be supplied to asubstrate. During the low power consumption mode, the substrate voltagegenerator steadily consuming the electric power stops so that the powerconsumption is drastically reduced.

According to another aspect of the semiconductor memory device in thepresent invention, in response to the control signal from the exterior,the entry circuit stops the operation of an internal supply voltagegenerator to stop the generation of an internal supply voltage to besupplied to a memory core. During the low power consumption mode, theinternal supply voltage generator steadily consuming the electric powerstops so that the power consumption is drastically reduced.

According to another aspect of the semiconductor memory device in thepresent invention, in response to the control signal from the exterior,the entry circuit stops the operation of a precharging voltage generatorto stop the generation of a precharging voltage to be supplied to bitlines. During the low power consumption mode, the precharging voltagegenerator steadily consuming the electric power stops so that the powerconsumption is drastically reduced.

According to another aspect of the semiconductor memory device in thepresent invention, an external voltage supplying circuit supplies thepower supply voltage as the internal voltage to the internal circuitduring the low power consumption mode. When the internal voltagegenerating circuit is inactive, therefore, the power supply terminal ofeach internal circuit is supplied with a predetermined power supplyvoltage. As a result, each element of the internal circuit is fixed in apredetermined state to prevent a leak path. In other words, the flow ofa feedthrough current is prevented.

According to another aspect of the semiconductor memory device in thepresent invention, a predetermined internal circuit is inactivated whena reset signal is supplied from the exterior. In response to this resetsignal, the entry circuit enters the device into the low powerconsumption mode. During the resetting, the device need not be operated.Therefore, it can enter the low power consumption mode by utilizing theexisting signal. The type and number of external terminals are identicalto those of the conventional terminals so that adding the low powerconsumption mode does not lower the usability.

According to another aspect of the semiconductor memory device in thepresent invention, the entry circuit receives a plurality of controlsignals from the exterior. The entry circuit enters the device into thelow power consumption mode when it recognizes the states of the controlsignals as low power consumption commands. Therefore, the device canenter the low power consumption mode by the command input.

According to another aspect of the semiconductor memory device in thepresent invention, the entry circuit receives a reset signal and a chipenable signal from the exterior. The entry circuit enters the deviceinto the low power consumption mode when it recognizes the states ofthose control signals as low power consumption commands. Therefore, thedevice can enter the low power consumption mode by the command input.

According to another aspect of the semiconductor memory device in thepresent invention, when the reset signal is inactivated during apredetermined period and in this state the chip enable signal isactivated during a predetermined period, the device enters the low powerconsumption mode. Even when a glitch occurs in the reset signal or thechip enable signal due to power supply noises or the like, it is able toprevent the device from erroneously entering the low power consumptionmode.

According to another aspect of the semiconductor memory device in thepresent invention, the entry circuit receives a plurality of controlsignals from the exterior during the low power consumption mode. Theentry circuit exits the device from the low power consumption mode whenthe levels of the control signals indicate exit of the low powerconsumption mode. Therefore, the device can be exited from the low powerconsumption mode by the command input.

The entry circuit enters the device into the low power consumption modewhen it receives the predetermined level or the transition edge of a lowpower consumption mode signal. Therefore, the device can reliably enterthe low power consumption mode by employing a dedicated signal.

According to another aspect of the semiconductor memory device in thepresent invention and controlling the semiconductor memory device, whenthe state of a control signal received during the low power consumptionmode indicates exit of the low power consumption mode, the low powerconsumption mode is exited. This allows the device to be easily exitedfrom the low power consumption mode by a control signal from theexterior. The exist from the low power consumption mode is, for example,executed by controlling the entry circuit.

According to another aspect of the semiconductor memory device in thepresent invention and controlling the semiconductor memory device, afterthe low power consumption mode is exited, a reset signal forinitializing an internal circuit is activated during a period where theinternal voltage is lower than a predetermined voltage. For instance,the reset signal is activated during a period where the internal voltageis lower than a reference voltage generated by stepping down the powersupply voltage. Therefore, when the low power consumption mode shifts toa normal operating mode, the internal circuit can be reliably reset,which prevents malfunction of the internal circuit.

According to another aspect of the semiconductor memory device in thepresent invention, after the low power consumption mode is exited, areset signal for initializing an internal circuit is activated during aperiod where a boost voltage internally generated is lower than apredetermined voltage. For example, the reset signal is activated duringa period where the boost voltage is lower than the power supply voltage.In addition, the reset signal can be activated during a period where theboost voltage is lower than a reference voltage generated by steppingdown the power supply voltage.

According to another aspect of the semiconductor memory device in thepresent invention, after the low power consumption mode is exited, areset signal for initializing an internal circuit is activated during aperiod where at least one of the internal voltage and a boost voltageinternally generated is/are lower than respective predeterminedvoltages. Therefore, when the low power consumption mode shifts to thenormal operating mode, the internal circuit can be reliably reset, whichprevents malfunction of the internal circuit.

According to another aspect of the semiconductor memory device in thepresent invention, at the time of the exit from the low powerconsumption mode, while a timer is measuring a predetermined length oftime, a reset signal for initializing an internal circuit is activated.This allows reliable reset of the internal circuit, leading topreventing malfunction of the internal circuit when the low powerconsumption mode shifts to a normal operating mode.

According to another aspect of the semiconductor memory device in thepresent invention, a timer includes a CR time constant circuit. Thetimer measures the length of a time based on the propagation delay timeof a signal propagated to the CR time constant circuit so that theactivation period of a reset signal can be set by a simple circuit.

According to another aspect of the semiconductor memory device in thepresent invention, at the time of the exit from the low powerconsumption mode, a reset signal for initializing an internal circuit isactivated while a counter operating in the normal operation counts apredetermined number. This allows reliable reset of the internalcircuit, leading to preventing malfunction of the internal circuit whenthe low power consumption mode shifts to a normal operating mode. Forexample, a refresh counter for indicating the refresh address of memorycells or the like is employed as a counter.

According to another aspect of the semiconductor memory device and themethod of controlling the semiconductor memory device in the presentinvention, a self-refresh control circuit automatically refreshes memorycells at a predetermined cycle. An internal voltage generator generatesan internal voltage to be supplied to a predetermined internal circuitupon receipt of a power supply voltage from the exterior. Thesemiconductor memory device when receiving a control signal from theexterior, inactivates the self-refresh control circuit and lowers thesupply capability of the internal voltage generator, thereby enteringinto a low power consumption mode. When the data of the memory cellsneed not be retained during the low power consumption mode, theoperations of the self-refresh control circuit are unnecessary. Owing tonot executing refresh, the internal voltage generator may operate with apower enough to compensate an electric power (leakage current) to beconsumed by the internal circuit. As a result, the power consumptionduring the low power consumption mode can be reduced.

The internal voltage is supplied to the internal circuit even during thelow power consumption mode. Therefore, the internal circuit can operateimmediately after a release from the low power consumption mode.

According to another aspect of the semiconductor memory device in thepresent invention, the internal voltage generator includes a pluralityof units for generating the internal voltage. During the low powerconsumption mode, a part of the units suspend(s) so that the powerconsumption during the low power consumption mode can be furtherreduced.

According to another aspect of the semiconductor memory device and themethod of controlling the semiconductor memory device in the presentinvention, a stabilized capacitor connected with a power supply linestores a portion of electric charge to be supplied to the power supplyline. The semiconductor memory device when receiving a control signalfrom the exterior, keeps a connection between the power supply line andthe stabilized capacitor but disconnects the power supply line and theinternal circuit, thereby entering into the low power consumption mode.Therefore, the power consumption of the internal circuit can be reducedto zero during the low power consumption mode. After the release fromthe low power consumption mode, the voltage corresponding to theelectric charge stored in the stabilized capacitor is applied to theinternal circuit through the power supply line when the power supplyline and the internal circuit are connected. As a result, thesemiconductor memory device can operate immediately after the releasefrom the low power consumption mode.

According to another aspect of the semiconductor memory device in thepresent invention, an internal voltage generator generates an internalvoltage upon receipt of a power supply voltage from the exterior. Theinternal voltage is supplied to the internal circuit through the powersupply line. After the release from the low power consumption mode,therefore, the voltage corresponding to the electric charge stored inthe stabilized capacitor can be supplied to the internal circuit.

According to another aspect of the semiconductor memory device and themethod of controlling the semiconductor memory device in the presentinvention, an internal voltage generator generates an internal voltageto be supplied to a predetermined internal circuit, upon receipt of apower supply voltage from the exterior. An internal voltage detectordetects the level of the internal voltage and controls the internalvoltage generator according to its detection result. The semiconductormemory device receiving a control signal from the exterior, weakens theresponse of the internal voltage detector, thereby entering to a lowpower consumption mode. Weakening the response of the internal voltagedetector results in lowering the operation frequency of the internalvoltage generator to be operated under the control of the internalvoltage detector. As a result, the power consumption during the lowpower consumption mode can be reduced.

According to another mode of the semiconductor memory device of theinvention, the internal voltage generator includes a plurality of unitsfor detecting the level of the internal voltage. During the low powerconsumption mode, a part of the units suspend(s) their operations sothat the power consumption during the power consumption mode can befurther reduced.

According to another aspect of the semiconductor memory device and themethod of controlling the semiconductor memory device in the presentinvention, an internal voltage generator generates an internal voltageto be supplied to a predetermined internal circuit, upon receipt of apower supply voltage from the exterior. An internal voltage detectordetects the level of the internal voltage and controls the internalvoltage generator according to its detection result. The semiconductormemory device receiving a control signal from the exterior, lowers thedetection level of the internal voltage in the internal voltage detectorand reduces the absolute value of the internal voltage generated by theinternal voltage generator, thereby entering into a low powerconsumption mode. Therefore, the drivability of the internal voltagegenerator can be lowered, which reduces the power consumption.

According to another aspect of the semiconductor memory device in thepresent invention, a reference voltage generator generates a referencevoltage. The internal voltage detector detects the level of the internalvoltage by comparing the internal voltage with the reference voltage.The semiconductor memory device receiving a control signal from theexterior, lowers the level of the reference voltage generated by thereference voltage generator, thereby decreasing the absolute value ofthe detection level of the internal voltage in the internal voltagedetector. This results in reducing the absolute value of the level ofthe internal voltage and the off current of transistors and so on in theinternal circuit, thereby reducing the power consumption.

According to another aspect of the semiconductor memory device and themethod of controlling the semiconductor memory device in the presentinvention, a self-refresh control circuit automatically refreshes memorycells at a predetermined cycle. When the semiconductor memory devicereceives a control signal from the exterior, it inactivates theself-refresh control circuit and enters into a low power consumptionmode. Owing to not executing refresh during the low power consumptionmode, a current amount consumed for the refresh can be reduced.

According to another aspect of the semiconductor memory device in thepresent invention, the self-refresh control circuit includes a timer fordetermining a length of refresh cycle. The timer suspends during the lowpower consumption mode so that the power consumption can be reduced.

According to one aspect of a method of controlling the semiconductormemory device in the present invention, the internal voltage generatorwhen activated, generates the internal voltage to be supplied to apredetermined internal circuit. When the internal voltage generator isoperated, a predetermined amount of electric power is consumed. Inresponse to the control signal from the exterior, the internal voltagegenerator is inactivated. The internal voltage is not to be generateddue to the inactivation of the internal voltage, which results inreducing the power consumption. In response to the control signal fromthe exterior, therefore, the device can easily enter the low powerconsumption mode.

According to another aspect of the method of controlling thesemiconductor memory device in the present invention, a plurality ofcontrol signals is received from the exterior. The device enters the lowpower consumption mode when it recognizes the states of the controlsignals as the low power consumption commands. Therefore, the device canenter the low power consumption mode by the command input.

According to another aspect of the method of controlling thesemiconductor memory device in the present invention, when the powersupply is switched on, the chip enable signal remains inactivated untilthe power supply voltage reaches a predetermined voltage. This makes itpossible to prevent an erroneous entry to the low power consumption modewhen the power supply is switched on.

BRIEF DESCRIPTION OF THE DRAWINGS

The nature, principle, and utility of the invention will become moreapparent from the following detailed description when read inconjunction with the accompanying drawings in which like parts aredesignated by identical reference numbers, in which:

FIG. 1 is a state transition diagram of a semiconductor memory device ofthe present invention;

FIG. 2 is a block diagram showing a basic principle of a firstembodiment;

FIG. 3 is a block diagram showing the first embodiment;

FIG. 4 is a circuit diagram showing the details of a booster and aprecharging voltage generator of FIG. 3;

FIG. 5 is a circuit diagram showing the details of an internal supplyvoltage generator and a substrate voltage generator of FIG. 3;

FIG. 6 is a circuit diagram showing the detail of an essential portionof a memory core of FIG. 3;

FIG. 7 is a timing chart showing the operations of the first embodimentat the switch-on of a power supply and at the times of entry into andexit from a low power consumption mode;

FIG. 8 is a block diagram showing an example in which the semiconductormemory device of the first embodiment is used in a cellular phone;

FIG. 9 is an explanatory diagram showing the state of using the cellularphone shown in FIG. 8;

FIG. 10 is a flow chart showing the state of controlling the cellularphone shown in FIG. 8;

FIG. 11 is a block diagram showing a second embodiment;

FIG. 12 is a circuit diagram showing the detail of a low power entrycircuit of FIG. 11;

FIG. 13 is a timing chart showing the operations of the low power entrycircuit of FIG. 12;

FIG. 14 is a block diagram showing a third embodiment;

FIG. 15 is a circuit diagram showing a VII starter in a fourthembodiment;

FIG. 16 is a circuit diagram showing a VII starter in the fourthembodiment;

FIG. 17 is a timing chart showing operations at the entry to and theexit from a low power consumption mode in the fourth embodiment;

FIG. 18 is a circuit diagram showing a level detecting circuit in afifth embodiment;

FIG. 19 is a timing chart showing operations at the entry to and theexit from a low power consumption mode in the fifth embodiment;

FIG. 20 is a circuit diagram showing a start signal generator in a sixthembodiment; and

FIG. 21 is a timing chart showing operations at the entry to and theexit from a low power consumption mode in the sixth embodiment.

FIG. 22 is a block diagram showing a seventh embodiment;

FIG. 23 is a circuit diagram showing the detail of a reference voltagegenerator of FIG. 22;

FIG. 24 is a circuit diagram showing the detail of an internal supplyvoltage generator of FIG. 22;

FIG. 25 is a block diagram showing a booster, a VPP detector, asubstrate voltage generator and a VBB detector;

FIG. 26 is a circuit diagram showing the detail of a unit of the boosterof FIG. 25;

FIG. 27 is a circuit diagram showing the detail of the unit of thebooster of FIG. 25;

FIG. 28 is a circuit diagram showing the detail of the VPP detector ofFIG. 22;

FIG. 29 is a circuit diagram showing the detail of a unit of thesubstrate voltage generator of FIG. 25;

FIG. 30 is a circuit diagram showing the detail of the unit of thesubstrate voltage generator of FIG. 25;

FIG. 31 is a circuit diagram showing the detail of the VBB detector ofFIG. 22;

FIG. 32 is a circuit diagram showing the detail of a precharging voltagegenerator of FIG. 22;

FIG. 33 is a circuit diagram showing the detail of an oscillator of FIG.22;

FIG. 34 is a circuit diagram showing the detail of a generator of FIG.23; and

FIG. 35 is a timing chart showing the operations of the oscillator and afrequency divider in the seventh embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described with reference tothe accompanying drawings.

FIG. 1 shows a state transition diagram of a semiconductor memory deviceof the present invention.

First of all, the semiconductor memory device comes into an idle modewhen the power supply is switched on. When a read command or a writecommand is received in the idle mode, the mode shifts to an operatingmode to execute a read operation or a write operation. After theexecution of the read operation or the write operation, the idle mode isautomatically restored. When a self-refreshing command is received inthe idle mode, the device enters the self-refreshing mode to executeself-refresh. Herein the self-refreshing mode, a refresh address isautomatically generated to sequentially execute refreshing operations inmemory cells.

The semiconductor memory device enters the low power consumption mode bydetecting a predetermined state of a signal in the idle mode. In a firstembodiment described below, in response to a chip enable signal CE2, thedevice enters the low power consumption mode. Specifically, by the chipenable signal CE2 a predetermined internal circuit is inactivated andthe device enters the low power consumption mode. In a second embodimentdescribed below, in response to a command input by chip enable signals/CE1 and CE2, the device enters the low power consumption mode. In athird embodiment described below, in response to a dedicated low powerconsumption mode signal /LP, the device enters the low power consumptionmode.

The semiconductor memory device detects a predetermined state of asignal during the low power consumption mode and exits the mode.

FIG. 2 shows the basic principle of the semiconductor memory device ofthe present invention.

The semiconductor memory device includes an entry circuit 1, an internalvoltage generator 2, an external voltage supplying circuit 3, and aninternal circuit 4.

The internal voltage generator 2 generates an internal voltage in eachmode after the power supply is switched on, and supplies the internalvoltage to the internal circuit 4. The entry circuit 1 receives acontrol signal and inactivates the internal voltage generator 2 when itdetects a predetermined state of the control signal. When the internalvoltage generator 2 is inactivated, the generation of the internalvoltage is stopped. At the same time, the entry circuit 1 activates theexternal voltage supplying circuit 3. This external voltage supplyingcircuit 3 supplies the power supply voltage as the internal voltage tothe internal circuit 4. And, the semiconductor memory device enters thelow power consumption mode.

FIG. 3 shows a first embodiment of the semiconductor memory device andits control method in the present invention. The semiconductor memorydevice of this embodiment is formed as a DRAM on a p-type siliconsubstrate by employing the CMOS process technology.

The DRAM is provided with a VII starter 10, a VDD starter 12, a lowpower entry circuit 14, a command decoder 16, an internal voltagegenerator 18 and a main circuit unit 20. The internal voltage generator18 has a low-pass filter 22, a reference voltage generator 24, a VDDsupplying circuit 26, a booster 28, a precharging voltage generator 30,an internal supply voltage generator 32, a substrate voltage generator34 and a VSS supplying circuit 36. The main circuit unit 20 has a memorycore 38 and a peripheral circuit 40. Here, the low power entry circuit14 corresponds to the entry circuit 1 shown in FIG. 2, and the VDDsupplying circuit 26 and the VSS supplying circuit 36 correspond to theexternal voltage supplying circuit 3 shown in FIG. 2.

The DRAM is supplied with a power supply voltage VDD (e.g., 2.5 V) fromthe exterior, a ground voltage VSS, chip enable signals /CE1 and CE2 asthe control signals, a plurality of address signal AD, a plurality ofdata input/output signals DQ, and another control signal CN. This DRAMdoes not adopt the address multiplex method. Therefore, the addresssignals AD is supplied once at each read operation and at each writeoperation. The power supply voltage VDD and the ground voltage VSS aresupplied to almost all the circuits excepting a partial circuit of thememory core 38. Here, the signals headed by the letter “/” are those ofnegative logic. The “address signals AD” may be abbreviated into the “ADsignals” in the following description by omitting its signal name.

The /CE1 signal is turned to a low level when the read operation and thewrite operation are executed to activate the DRAM. The CE2 signalfunctions as a reset signal to inactivate a predetermined internalcircuit in the main circuit unit 20 when at the low level. The VIIstarter 10 receives the internal supply voltage VII and the groundvoltage VSS and outputs a start signal STTVII to the main circuit unit20. The VII starter 10 is resets the main circuit unit 20 after thepower supply is switched on until the internal supply voltage VIIreaches a predetermined voltage, and it prevents the malfunction of themain circuit unit 20. The VDD starter 12 receives the power supplyvoltage VDD and the ground voltage VSS and outputs a start signalSTTCRX. The VDD starter 12 inactivates the low power entry circuit 14after the power supply is switched on until the power supply voltage VDDreaches a predetermined voltage and it prevents the malfunction of thecircuit 14.

The low power entry circuit 14 receives the start signal STTCRX and theCE2 signal and activates a low power signal ULP.

In response to the /CE1 signal and another control signal CN, thecommand decoder 16 decodes a command and outputs the decoded command asan internal command signal to the peripheral circuit 40.

The low-pass filter 22 has a function to filter out the noise containedin the power supply voltage VDD. The power supply voltage VDD thuscleared of the noise is fed to the reference voltage generator 24 or thelike. In the low power consumption mode, the switch in the low-passfilter 22 is switched off and the power supply voltage VDD is notsupplied to the reference voltage generator 24 so that the current isnot consumed.

The reference voltage generator 24 receives the power supply voltage VDDand generates reference voltages VPREF (e.g., 1.5 V), VPRREFL (e.g., 0.8V), VPRREFH (e.g., 1.2 V) and VRFV (e.g., 2.0 V).

The VDD supplying circuit 26 turns a boost voltage VPP and an internalsupply voltage VII to the power supply voltage VDD during the low powerconsumption mode.

The booster 28 receives the reference voltage VPREF and generates theboost voltage VPP (e.g., 3.7 V) and supplies the boost voltage VPP tothe memory core 38.

The precharging voltage generator 30 receives the reference voltageVPRREFL and the reference voltage VPRREFH and generates a prechargingvoltage VPR (e.g., 1.0 V) to be supplied to the memory core 38.

The internal supply voltage generator 32 receives the reference voltageVRFV and generates the internal supply voltage VII (e.g., 2.0 V) to besupplied to the memory core 38 and the peripheral circuit 40.

The substrate voltage generator 34 receives the reference voltage VRFVand generates a substrate voltage VBB (e.g., −1.0 V) to be fed to thesubstrate and the p-wells of the memory cells.

The VSS supplying circuit 36 turns the precharging voltage VPR and thesubstrate voltage VBB to the ground voltage VSS during the low powerconsumption mode.

FIG. 4 shows the details of the booster 28 and the precharging voltagegenerator 30.

The booster 28 is composed of resistors R1 and R2 connected in series, adifferential amplifier 28 a, a pumping circuit 28 b, an nMOS 28 c, and aswitching circuit 28 d for controlling the gate of the nMOS 28 c. Theresistor R1 is supplied at its one end with the boost voltage VPP, andthe resistor R2 is supplied at its one end with the ground voltage VSSthrough the nMOS 28 c. A divided voltage V1 is generated from theconnection node of the resistors R1 and R2. The nMOS 28 c receives thepower supply voltage VDD from the switching circuit 28 d during the lowpower consumption mode. The differential amplifier 28 a is formed of aMOS differential amplifier using a current mirror circuit, for example,as the current source. The differential amplifier 28 a outputs a highlevel when the voltage V1 is lower than the reference voltage VPREF. Thepumping circuit 28 b receives the high level from the differentialamplifier 28 a and starts a pumping operation. By this pumpingoperation, the voltage VPP is raised, and the voltage V1 is raised. Whenthis voltage V1 coincides with the reference voltage VPREF (i.e., 1.5V), the output of the differential amplifier 28 a reaches the low levelso that the pumping operation stops. By repeating these operations, theboost voltage VPP is retained at a constant voltage.

The precharging voltage generator 30 is composed of two differentialamplifiers 30 a and 30 b connected at their outputs with each other. Thedifferential amplifier 30 a is supplied with the reference potentialVPRREFL and the precharging voltage VPR. The differential amplifier 30 bis supplied with the reference potential VPRREFL and the prechargingvoltage VPR. Moreover, these differential amplifiers 30 a and 30 bgenerate the precharging voltage VPR at an intermediate value betweenthe reference voltages VPRREFL and VPRREFH.

FIG. 5 shows the details of the internal supply voltage generator 32 andthe substrate voltage generator 34. The internal supply voltagegenerator 32 is composed of a negative feedback type differentialamplifier 32 a, a compensating circuit 32 b, a regulator 32 c made of annMOS, an nMOS 32 d, and a switching circuit 32 e for controlling thegate of the nMOS. The differential amplifier 32 a receives the referencevoltage VRFV and a voltage V2 generated by the compensating circuit 32b, and supplies a predetermined voltage to a node VG. In thecompensating circuit 32 b, an nMOS and resistors R3 and R4 in a diodeconnection are arranged in series between the node VG and the groundline VSS. The voltage V2 is generated at the connection node between theresistors R3 and R4. The regulator 32 c is connected at its gate withthe node VG, receives the power supply voltage VDD at its drain andgenerates the internal supply voltage VII at its source.

The nMOS 32 d is grounded at its source and connected at its drain withthe node VG. The switching circuit 32 e supplies the power supplyvoltage VDD to a gate of the nMOS 32 d during the lower powerconsumption mode. The nMOS 32 d receives the power supply voltage VDDfrom the switching circuit 32 e during the low power consumption mode,and fixes the node VG at the ground level.

In this internal supply voltage generator 32, when the threshold voltageof the regulator 32 c is lowered due to the rise in the ambienttemperature, for example, the threshold voltage of the nMOS of thecompensating circuit 32 b also drops, so that the voltage V2 rises. Inresponse to the rise in the voltage V2, the differential amplifier 32 alowers the voltage of the node VG. Moreover, the source-to-drain currentof the nMOS 32 c is made constant so that the internal supply voltageVII is made constant.

The substrate voltage generator 34 is composed of an oscillator 34 a anda pumping circuit 34 b. In response to the high level of a controlsignal VBBEN, the oscillator 34 a starts the oscillating operation tooutput an oscillating signal OSC. The pumping circuit 34 b has acapacitor for repeating charge and discharge in response to theoscillating signal OSC from the oscillator 34 a, and a diode-connectednMOS transistor connected with one end of the capacitor. The charges ofa p-type substrate connected with the anode are discharged by thepumping operation, which lowers the substrate voltage VBB. Making thesubstrate voltage VBB negative leads to gaining some effects such asreducing the influences of a shift in the threshold voltage of thememory cells due to the substrate effect so that the characteristics ofthe memory cells may be improved.

FIG. 6 shows the detail of an essential portion of the memory core 38.

The memory core 38 has a memory cell MC, nMOS switches 42 a and 42 b, aprecharging circuit 44 and a sense amplifier 46.

The memory cell MC is composed of a data transferring nMOS and acapacitor. The gate of the nMOS is connected with a word line WL0 (orWL1).

The nMOS switches 42 a and 42 b control the connection between a bitline BL (or /BL) on the side of the memory cell MC and a bit line BL (or/BL) on the side of a sense amplifier SA. The nMOS switches 42 a and 42b receive a control signal BT at their gates.

The precharging circuit 44 is composed of three nMOSes 44 a, 44 b and 44c. The nMOS 44 a is connected at its source and drain, respectively,with the bit lines BL and /BL. The nMOSes 44 b and 44 c are connected atone of their sources and drains, respectively, with the bit lines BL and/BL, and are supplied at their others with the precharging voltage VPR.The nMOSes 44 a and 44 b and 44 c receive a bit line control signal BRSat their gates.

The sense amplifier 46 is constructed by connecting the inputs andoutputs of two CMOS inverters with each other. Each of these CMOSinverters is connected at its outputs individually with the bit lines/BL and BL. The source of the pMOS and the source of the nMOS of eachCMOS inverter are connected with power supply lines PSA and NSA,respectively. The voltages of these power supply lines PSA and NSAindividually reach the VPR level during a standby state and during theinactivation of the sense amplifiers, and respectively change to theinternal supply voltage VII and the ground voltage VSS when the bitlines are amplified.

FIG. 7 shows the operations of the switch-on of the power supply, theshifting (entry) to the low power consumption mode, and the release(exit) from the low power consumption mode with regard to theaforementioned semiconductor memory device.

First of all, when the power supply is switched on, the power supplyvoltage VDD rises gradually (FIG. 7( a)). The VDD starter 12 shown inFIG. 3 inactivates the start signal STTCRX (to the low level) till thepower supply voltage VDD reaches a predetermined voltage (FIG. 7( b)).

By this control, it is possible to prevent the ULP signal from beingactivated due to the malfunctioning of the low power entry circuit 14when the power supply is switched on. An exterior controller (e.g., aCPU or a memory controller) for controlling the DRAM turns the CE2signal at the high level a predetermined time T0 after the power supplyvoltage VDD reaches the minimum operable voltage VDDmin (FIG. 7( c)).

After this, the DRAM becomes the standby state or executes an ordinaryoperation. The exterior controller turns the CE2 signal to the low levelwhen the DRAM enters the low power consumption mode (FIG. 7( d)). Thelow power entry circuit 14 activates the ULP signal (to the high level)in response to the fall of the CE2 signal when the STTCRX signal is atthe high level (FIG. 7( e)).

In response to the high level of the ULP signal, the low-pass filter 22of the internal voltage generator 18 stops the supply of the powersupply voltage to the reference voltage generator 24 and insteadsupplies the ground voltage VSS from the VSS supplying circuit 36. Inresponse to the ground voltage VSS, the reference voltage generator 24turns the reference voltages VPREF, VPRREFL, VPRREFH and VRFV to theground level. The nMOS 28 b of the booster 28 shown in FIG. 4 and thenMOS 32 d of the internal supply voltage generator 32 shown in FIG. 5are switched off. As a result, the booster 28, the precharging voltagegenerator 30, the internal supply voltage generator 32 and the substratevoltage generator 34 are inactivated to stop their operations. Thus, allthe conventional circuits remaining operative during the low powerconsumption mode are stopped. Therefore, the power consumption in thelow power consumption mode is drastically reduced as compared with theconventional.

When these circuits are inactivated, the generations of the boostvoltage VPP, the precharging voltage VPR, the internal supply voltageVII and the substrate voltage VBB are stopped. However, the boostvoltage VPP and the internal supply voltage VII are changed into thepower supply voltage VDD by the VSS supplying circuit 36, and thesubstrate voltage VBB and the precharging circuit VPR are changed intothe ground voltage VSS by the VSS supplying circuit 36. Therefore, theinternal circuit of the main circuit unit 20 is prevented from having aleak path.

The exterior controller turns the CE2 signal to the high level when thelow power consumption mode is released (FIG. 7( f)). In response to thehigh level of the CE2 signal, the low power entry circuit 14 inactivatesthe ULP signal (to the low level) (FIG. 7( g)). In response to theinactivation of the ULP signal, the low-pass filter 22 supplies thepower supply voltage VDD to the reference voltage generator 24. Inresponse to the inactivation of the ULP signal, the VDD supplyingcircuit 26 and the VSS supplying circuit 36 stop the supplies of thepower supply voltage VDD and the ground voltage VSS. Then, the booster28, the precharging voltage generator 30, the internal supply voltagegenerator 32 and the substrate voltage generator 34 are activated againto start their operations.

Here, the DRAM enters the idle mode a time T1 after the high level ofthe CE2 signal. This time T1 is a time required for the individualinternal voltages VPP, VPR, VII and VBB to become stable.

FIG. 8 shows an example in which the semiconductor memory device of thefirst embodiment is employed in a cellular phone.

This cellular phone has the DRAM of this embodiment, the CPU and theflash memory mounted on the circuit board.

The CPU controls the read/write operation of the data from/in the DRAMand the flash memory. The DRAM is employed as the work memory, and theflash memory is employed as the backup memory when the cellular phone isswitched off or in the waiting state.

FIG. 9 shows the state of using the cellular phone shown in FIG. 8.

In this example, the DRAM is in the low power consumption mode by thecontrol of the CPU when the cellular phone is in the waiting state. Atthis time, the power consumption of the DRAM is as much as that of theflash memory in the standby state.

When the cellular phone then enters the service state from the waitingstate, the CPU raises the CE2 signal shown in FIG. 8 to the high level.After the DRAM entered the idle mode, the data retained in the flashmemory are transferred to the DRAM (FIG. 9( a)). During the servicestate, the DRAM is used as the work memory. Here, the service stateincludes not only the state of exchanging vocal communications but alsothe state of transferring data.

When the service state shifts to the waiting state, those, of the dataof the DRAM, necessary to be retained are saved in the flash memory(FIG. 9( b)). After this, the CPU lowers the CE2 signal to the low leveland enters the DRAM to the low power consumption mode. The DRAM does notperform refresh operation in the low power consumption mode so that theunnecessary data is lost.

When the power supply is switched off, the necessary data are retainedin the flash memory. By applying the DRAM of the first embodiment to thework memory of the cellular phone, the power consumption when thecellular phone is in the waiting state is drastically reduced.

Here, the DRAM and the flash memory may be controlled not by the CPU butby a dedicated memory controller or the like. The data transfer may alsobe done during the service state if necessary not only when theswitching over the waiting state and the service state. Moreover, thememory for backing up the data should not be limited to the flash memorybut may be an SRAM. The data may be saved in a server such as the basestation of the cellular phone.

FIG. 10 is a flow chart showing a control of the cellular phone shown inFIG. 8. At first Step S1, an entry to the low power consumption mode isprevented when the power supply is switched on. As shown in FIG. 7,specifically, the malfunction is prevented during the activation periodof the STTCRX signal of the VDD starting circuit 12.

Next, at Step S2, the CPU turns the CE2 signal to the low level to enterthe DRAM into the low power consumption mode. At Step S3, the cellularphone is in the waiting state.

Next, at Step S4, the CPU detects whether or not the power supply isswitched off. When the power supply is switched off, the procedure iscomplete. When the power supply is not switched off, the procedureadvances to Step S5.

At Step S5, the CPU repeats the waiting state until it becomes theservice state. When it becomes the service state, the procedure advancesto Step S6.

At Step S6, the CPU raises the CE2 signal to the high level to shift theDRAM from the low power consumption mode to the idle mode. Then, theindividual power supply circuits 28, 30, 32 and 34 shown in FIG. 3 arestarted again.

Next, at Step S7, the CPU transfers the data retained in the flashmemory to the DRAM (return the data).

Next, at Step S8, the service or the data transfer is performed.

At Step S9, the CPU detects whether or not the DRAM becomes the waitingstate. When it does not, the procedure returns to Step S7. When it does,the procedure advances to Step S10.

At Step S10, the CPU transfers those of the data of the DRAM necessaryto be retained, to the flash memory (save the data).

Then, the procedure returns to Step S2, at which the cellular phoneenters again the waiting state. The DRAM enters the low powerconsumption mode.

In the semiconductor memory device and its control method of the presentinvention, the operations of the booster 28, the precharging voltagegenerator 30, the internal supply voltage generator 32 and the substratevoltage generator 34 are stopped during the low power consumption mode.Therefore, the power consumption in the low power consumption mode canbe drastically reduced, as compared with the conventional.

In the low power consumption mode, the boost voltage VPP and theinternal supply voltage VII, and the substrate voltage VBB and theprecharging voltage VPR are set at the power supply voltage VDD and theground voltage VSS, respectively. Therefore, the internal circuit of themain circuit unit 20 can be prevented from having the leak path therebyto reduce the power consumption.

By utilizing the CE2 signal existing in the conventional, the DRAM isentered to the low power consumption mode. Therefore, the kind and thenumber of the external terminals can be identical to those of theconventional terminals. As a result, the user of the DRAM is notrequired to drastically change the circuit due to adding the low powerconsumption mode.

When the power supply is switched on, the VDD starter 12 inactivates thestart signal STTCRX (to the low level) until the power supply voltageVDD reaches the predetermined voltage. As a result, the low power entrycircuit 14 can be prevented from any malfunction when the power supplyis switched on, to prevent the ULP signal from being activated and theDRAM from entering the low power consumption mode.

When the power supply is switched on, the CE2 signal is raised to thehigh level the predetermined time T0 after the power supply voltage VDDreaches the minimum operating voltage VDDmin. This makes it possible toprevent the erroneous entry into the low power consumption mode when thepower supply is switched on.

By applying the DRAM of the present invention to the work memory of thecellular phone, therefore, the power consumption of the cellular phoneduring the waiting state can be drastically reduced. Moreover, themalfunction can be prevented.

FIG. 11 shows a second embodiment of the semiconductor memory device andits control method of the present invention. The same circuits as thosedescribed in the first embodiment are designated by the common referencenumerals, and their detailed description will be omitted.

In this embodiment, a low power entry circuit 50 is supplied with the/CE1 signal and the CE2 signal. A command decoder 52 is supplied withthe /CE1 signal, the CE2 signal and another control signal CN. Theremaining construction is identical to that of foregoing firstembodiment.

FIG. 12 shows the detail of the low power entry circuit 50.

The low powder entry circuit 50 has timing adjusting circuits 54 a and54 b, a level shifter 56, an RS flip-flop 58 and a combinational circuit60.

The timing adjusting circuit 54 a is formed by connecting a two-inputNOR gate connected at its one input with a delay circuit 54 c and atwo-input NAND gate connected at its one input with the delay circuit 54c, in plurality in cascade. Each delay circuit 54 c has an MOS capacityarranged between a plurality of inverters connected in cascade. Thetiming adjusting circuit 54 a delays the falling edge of a chip enablesignal CE2Z by about 100 ns and outputs it to a node ND1. The CE2Zsignal is the CE2 signal which is supplied from the exterior andreceived at the input buffer (not shown).

The timing adjusting circuit 54 b is identical to the timing adjustingcircuit 54 a. The timing adjusting circuit 54 b delays the falling edgeof the signal transmitted to a node ND3, by about 100 ns.

The level shifter 56 has two sets of pMOSes and nMOSes connected inseries. Each nMOS receives at its gate the signals in phase and ininverted phase of a row address strobe signal RASX. The inverter forgenerating these inverted and uninverted signals of the RASX signalreceives the internal supply voltage VII and the ground voltage VSS. TheRASX signal is a control signal which turns to a low level when the wordline is activated. The gates of the pMOSes are individually connectedwith the drains of the adjacent pMOSes, and the drains (or output nodes)of the nMOSes for receiving the positive logic of the RASX signal areconnected with the RS flip-flop 58. Each pMOS receives the power supplyvoltage VDD at its source, and each nMOS receives the ground voltage VSSat its source.

The RS flip-flop 58 is composed of two two-input NOR gates. One inputcorresponding to an output node ND2 receives the start signal STTCRX,and the other input receives the output signal of the level shifter 56.

The combinational circuit 60 receives the low level of the nodes ND1,ND2 and the chip enable signal CE1X and it turns the output node ND3 atthe low level. The CE1X signal is generated at the input buffer (notshown) receiving the /CE1 signal supplied from the exterior and is alsothe negative logic signal.

The timing adjusting circuit 54 b activates the ULP signal (to the highlevel) through the inverter about 100 ns after receiving the low levelof the node ND3.

FIG. 13 shows the operations of the low power entry circuit 50.

First, when the power supply is switched on, the STTCRX signal turns tothe low level so that the voltage of the /CE1 signal rises following thepower supply voltage VDD. Thus, the malfunction is prevented.

A predetermined time after the power supply was switched on, the STTCRXsignal turns to the high level (FIG. 13( a)). After this, the exteriorcontroller for controlling the DRAM raises the CE2 signal to the highlevel (FIG. 13( b)). The timings above are identical to those of thefirst embodiment. In response to the high level of the CE2Z signal, thenode ND1 shown in FIG. 12 turns to the high level (FIG. 13( c)).

The initial cycle is executed to turn the RASX signal to the low level(FIG. 13( d)). In response to the low level of the RASX signal, the RSflip-flop 58 raises the node ND2 to the high level (FIG. 13( e)). Afterthis, there are started the operations of the internal voltage generator18 shown in FIG. 11.

Next, there is supplied an entry command for the entry into the lowpower consumption mode. In this embodiment, the DRAM enters the lowpower consumption mode by turning the /CE1 signal to the low level apredetermined time after turning the CE2 signal to the low level.

The timing adjusting circuit 54 a turns the node ND1 to the low levelabout 100 ns after receiving the low level of the CE2Z signal (FIG. 13(f)). 100 ns or more after the falling edge of the CE2Z signal, the CE1Xsignal is turned to the low level (FIG. 13( g)). In response to the lowlevel of the CE1 Z signal and the low level of the node ND1, thecombinational circuit 60 shown in FIG. 12 turns the node ND3 to the lowlevel (FIG. 13( h)). The timing adjusting circuit 54 b raises the ULPsignal to the high level (FIG. 13( i)) about 100 ns after receiving thelow level of the node ND3. The DRAM enters the low power consumptionmode.

Thus, the DRAM enters the low power consumption mode by the commandinput.

At this time, the inverter of the level shifter 56 shown in FIG. 12receives the power supply voltage VDD in place of the internal supplyvoltage VII. As a result, the level shifter 56 is prevented to have theleak path because the gate of the nMOS is reliably switched off.

When the low power consumption mode is released, the CE1X signal isfirst turned to the high level (FIG. 13( j)). The combinational circuit60 receives the high level of the CE1X signal to turn the node ND3 tothe high level (FIG. 13( k)) and the ULP signal to the low level (FIG.13( l)). 200 μs after the rising edge of the CE1X signal, the CE2Zsignal is turned to the high level (FIG. 13( m)). In response to thehigh level of the CE2Z signal, a level of the node ND1 turns to the highlevel. During this period of 200 μs, the internal voltage generator 18is activated to stabilize the individual internal voltages VPP, VPR, VIIand VBB at predetermined levels.

Here, the activations and inactivations of the internal voltagegenerator 18 are performed as in the first embodiment. Specifically, thecontrols of the individual circuits in this embodiment are identical tothose of the first embodiment excepting that the entry to and exit fromthe low power consumption mode are executed by the command inputs.

This embodiment can achieve effects similar to those of the foregoingfirst embodiment. In this embodiment, moreover, the DRAM can enter thelow power consumption mode and can be released from the low powerconsumption mode by the command inputs using the /CE1 signal and the CE2signal.

FIG. 14 shows a third embodiment of the semiconductor memory device ofthe present invention. The same circuits as those described in the firstand second embodiments are designated by the common reference numerals,and their detailed description will be omitted.

In this embodiment, a low power entry circuit 62 receives the low powerconsumption mode signal /LP. This low power consumption mode signal /LPis a signal dedicated for the DRAM to enter the low power consumptionmode. The low power entry circuit 62 detects the falling edge of the /LPsignal to bring the DRAM into the low power consumption mode. Thecommand decoder 52 is supplied with the /CE1 signal, the CE2 signal andanother control signal CN. The remaining constructions are similar tothose of the foregoing first embodiment.

The operation timings of the DRAM at the switch-on of the power supplyand at the entry into and the exit from the low power consumption modeaccording to this embodiment are identical to those of the case in whichthe CE2 signal is replaced by the /LP signal in the timing chart shownin FIG. 7.

This embodiment can also achieve effects similar to those of theforegoing first embodiment. In this embodiment, moreover, the DRAM canreliably enter the low power consumption mode and be released from themode by the dedicated low power consumption mode signal /LP.

FIGS. 15 and 16 show a VII starter in a fourth embodiment of thesemiconductor memory device and a third embodiment of its control methodof the present invention. The same circuits as those described in thefirst embodiment are designated by the common reference numerals, andtheir detailed description will be omitted.

In this embodiment, a VII starter 70 is formed in replace of the VIIstarter 10 in FIG. 3 (the first embodiment). The other configuration isidentical to that in FIG. 3. In other words, the DRAM of this embodimentsimilar to that of FIG. 7 enters the low power consumption mode byturning the CE2 signal to low level during a high-level period of the/CE1 signal and it is released from the low power consumption mode byturning the CE2 signal to high level.

The VII starter 70 comprises a release detecting circuit 72 shown inFIG. 15, a level detecting circuit 74, and a power-on circuit 76 shownin FIG. 16. In FIGS. 15 and 16, a logic circuit is supplied with a powersupply voltage VDD except the circuit with a power supply voltageindicated.

A release detecting circuit 72 comprises a detecting circuit 72 a, alevel shifter 72 b, and a flip-flop 72 c. The detecting circuit 72 areceives a low power signal ULP shown in FIG. 3 and outputs the lowlevel of a pulse LPLS in synchronization with the falling edge of theULP signal. The level shifter 72 b converts the high level voltage(internal power supply voltage VII) of a row address strobe signal RASZto the external power supply voltage VDD and outputs a row addressstrobe signal RASX1 having inverted logic. The level shifter 72 b isidentical to the level shifter 56 shown in FIG. 12. Receiving a lowpulse from the detecting circuit 72 a, the flip-flop 72 c turns arelease signal REL to high level, and receiving a low level (RASZ=highlevel) from the level shifter 72 b, it turns the release signal REL tolow level.

In FIG. 16, a level detecting circuit 74 comprises a differentialamplifier 74 a including a current mirror circuit and an inverter row 74b which includes an odd number of inverters and receives the output ofthe differential amplifier 74 a. The differential amplifier 74 a isactivated during the high level of the release signal REL, compares aninternal power supply voltage VII with a reference voltage VREF, andoutputs the comparison result to an inverter row 74 b. A generator forthe internal power supply voltage VII generates a constant value of theinternal power supply voltage VII independent of the fluctuation of thepower supply voltage VDD supplied from the exterior. On the other hand,the reference voltage VREF varies depending on the fluctuation of thepower supply voltage VDD.

The output voltage of the differential amplifier 74 a goes low when theinternal power supply voltage VII is lower than the reference voltageVREF. The differential amplifier 74 a comprises a MOS capacitor 74 c forreceiving the reference voltage VREF in order to prevent its response toinsignificant fluctuation of the reference voltage VREF. In addition, annMOS 74 d for receiving the reference voltage VREF is disposed on a pathto a ground line VSS in order to limit the amount of current flow to theground line VSS and reduce the power consumption during the operation ofthe differential amplifier 74 a. The nMOS 74 d operates ashigh-resistance. An inverter 74 e in the initial stage of the inverterrow 74 b has an nMOS connected in serial so as to have the logicthreshold of an input signal in conformity with the output of thedifferential amplifier 74 a.

A power-on circuit 76 turns a start signal STT to high level during apredetermined period since the power supply voltage is supplied to theDRAM. An OR circuit 78, upon receiving the high level of a start signalSTTPZ or the high level of the start signal STT, outputs the high levelof a start signal STTVII (reset signal). The start signal STTVII,similarly to that of FIG. 3, is supplied to the main circuit unit 20 andinitializes a predetermined internal circuit.

FIG. 17 shows the operation timings of the above-described DRAM at thetime of entry to and exit from the low power consumption mode.

Firstly, when the CE2 signal (not shown) is turned to low level, theDRAM enters the low power consumption mode by a low power entry circuit14 shown in FIG. 3 and a generator for the internal power supply voltageVII terminates its operation. The internal power supply voltage VII (forexample, 2.0V in a normal operation) becomes equal to the power supplyvoltage VDD (for example, 2.5V)(FIG. 17( a)) and an ULP signal turns tohigh level (FIG. 17( b)).

Subsequently, the CE2 signal being turned to high level, the DRAM isreleased from the low power consumption mode and the ULP signal turns tolow level (FIG. 17( c)). In other words, the DRAM is released from thelow power consumption mode in accordance with the level of the CE2signal received during the low power consumption mode. The exit from thelow power consumption mode is controlled by the low power entry circuit14 shown in FIG. 3.

Receiving the falling edge of the ULP signal, the detecting circuit 72 ain FIG. 15 turns an LPLS signal to low level (pulse)(FIG. 17( d)).Receiving the low level of the LPLS signal, the flip-flop 72 c in FIG.15 turns the REL signal to high level (FIG. 17( e)).

Due to the exit from the low power consumption mode, a power supply lineof the internal power supply voltage VII and that of the power supplyvoltage VDD are disconnected and simultaneously the generator for theinternal power supply voltage VII initiates its operation. The internalpower supply voltage VII goes low for some time from the initiation ofthe generator (FIG. 17( f)). The differential amplifier 74 a in FIG. 16outputs low level to the inverter row 74 b when the internal powersupply voltage VII is lower than the reference voltage VREF (forexample, 1.25V). The inverter row 74 b, upon receiving the low level ofthe differential amplifier 74 a, outputs the high level of the STTPZsignal (FIG. 17( g)). The OR circuit 78, upon receiving the high levelof the STTPZ signal, turns a start signal STTVII to high level. Thestart signal STTVII functions as a reset signal and a predeterminedinternal circuit of the main circuit unit 20 shown in FIG. 3 isinitialized.

After the exit from the low power consumption mode, by issuing anoperation command to the DRAM, the RASZ signal is turned to high level(FIG. 17( h)) and the REL signal to low level (FIG. 17( i)). Thedifferential amplifier 74 a is inactivated due to the low level of theREL signal.

As described above, at the time of the exit from the low powerconsumption mode, the initialization of the internal circuit prevents itfrom malfunctioning when the operation of the internal circuit suppliedwith the internal power supply voltage VII cannot be ensured because ofthe internal power supply voltage VII lower than a predetermined voltage(reference voltage VREF).

In this embodiment above, when the state of the CE2 signal receivedduring the low power consumption mode indicates exit of the low powerconsumption mode, the low power consumption mode is released. Thisallows the easy exit of a chip from the low power consumption mode bythe control signal from the exterior.

At the exit from the low power consumption mode, the start signal STTVIIwhich is a reset signal for initializing an internal circuit isactivated during a period where the internal power supply voltage VII islower than the reference voltage VREF. This makes it possible tosecurely reset the internal circuit and prevent the malfunction of theinternal circuit when the low power consumption mode shifts to thenormal operating mode.

One control signal (CE2 signal) enables the entry of a chip to the lowpower consumption mode and the exit of a chip from the low powerconsumption mode.

FIG. 18 shows a level detecting circuit 80 in a fifth embodiment of thesemiconductor memory device and its control method of a fourthembodiment of the present invention. The same circuits as thosedescribed in the first and forth embodiments are designated by thecommon reference numerals, and their detailed description will beomitted.

In this embodiment, a level detecting circuit 80 is formed in replace ofthe level detecting circuit 74 described in the forth embodiment. Theother configuration is identical to that in the forth embodiment.

The level detecting circuit 80 comprises: a differential amplifier 80for comparing the internal power supply voltage VII with the referencevoltage VREF; an inverter row 80 b including an even number ofinverters; a differential amplifier 80 c for comparing a boost voltageVPP of a word line (not shown) with the power supply voltage VDD fromthe exterior; an inverter row 80 d including an even number ofinverters; and an NAND gate 80 e. The boost voltage VPP generated by abooster is formed inside of the chip. The differential amplifiers 80 aand 80 c are identical to the differential amplifier 74 a in FIG. 16 andare activated upon receipt of the high level of the REL signal. Theinverter rows 80 b and 80 d are constructed of the inverter in theinitial stage and the inverter in the second stage of the inverter row74 b in FIG. 16. The inverter row 80 b receives the output of thedifferential amplifier 80 a and outputs the received logic level to aNAND gate 80 e as a start signal STT1X. The inverter row 80 d receivesthe output of the differential amplifier 80 c and outputs the receivedlogic level to the NAND gate 80 e as a start signal STT2X. The NAND gate80 e operates as an OR circuit of negative logic and outputs a startsignal STTPZ.

FIG. 19 shows the operation timings of the above-described DRAM at thetime of entry to and exit from a low power consumption mode.

Firstly, when the CE2 signal (not shown) is turned to low level, theDRAM enters the low power consumption mode and a generator for theinternal power supply voltage VII and a generator for the boost voltageVPP terminate their operation. The internal power supply voltage VII(for example, 2.0V in the normal operation) and the boost voltage VPP(for example, 3.7V in the normal operation) become equal to the powersupply voltage VDD (for example, 2.5V)(FIG. 19( a)) and an ULP signalturns to high level (FIG. 18( b)).

Subsequently, the CE2 signal being turned to high level, the DRAM isreleased from the low power consumption mode and the ULP signal turns tolow level (FIG. 19( c)). The LPLS signal is turned to low level (pulse)as well as in FIG. 17 (FIG. 19( d)) and the REL signal is turned to highlevel (FIG. 19( e)).

Due to the exit from the low power consumption mode, the power supplyline of the internal power supply voltage VII and the power supply lineof the power supply voltage VDD are disconnected and the generator forthe internal power supply voltage VII initiates its operation. Theinternal power supply voltage VII goes low for some time from theinitiation of the generator (FIG. 19( f)). The low level of the STT1Xsignal is output during a period where the internal power supply voltageVII is lower than the reference voltage VREF (for example, 1.25V) (FIG.19( g)). Similarly, the connection between the power supply line of theboost voltage VPP and that of the power supply voltage VDD isdisconnected and the generator for the boost voltage VPP initiates itsoperation. The boost voltage VPP goes low for some time from theinitiation of the generator (FIG. 19( h)). The low level of the STT2Xsignal is output during a period where the boost voltage VPP is lowerthan the power supply voltage VDD (FIG. 19( i)).

The NAND gate 80 e in FIG. 18 outputs the high level of the STTPZ signalduring a period where the STT1X signal or the STT2X signal is at lowlevel (FIG. 19( j)). During the high level of the STTPZ signal, thestart signal STTVII (FIG. 16) is turned to high level. The start signalSTTVII functions as a reset signal and initializes a predeterminedinternal circuit of the main circuit unit 20 shown in FIG. 3.

After the exit from the low power consumption mode, the DRAM initiatesits operation, thereby the RASZ signal being turned to high level (FIG.19( k)) and the REL signal to low level (FIG. 19( l)) as well as in FIG.17. The differential amplifier 80 a and 80 c are inactivated due to thelow level of the REL signal.

This embodiment can also achieve effects similar to those of theforegoing fourth embodiment. In this embodiment, moreover, at the timeof the exit from the low power consumption mode a start signal STTVIIfor initializing an internal circuit is activated during a period wherethe boost voltage VPP internally generated is lower than the powersupply voltage VDD from the exterior. Specifically, at the time of theexit from the low power consumption mode, the start signal STTVII forinitializing an internal circuit is activated during a period where atleast one of the internal power supply voltage VII and is/arerespectively lower than the reference voltage VREF and the power supplyvoltage VDD. This makes it possible to securely reset the internalcircuit and prevent the malfunction of the internal circuit when the lowpower consumption mode shifts to the normal operating mode.

FIG. 20 shows a start signal generator of the semiconductor memorydevice in a sixth embodiment and its control method of a fifthembodiment of the present invention. The same circuits as thosedescribed in the first and forth embodiments are designated by thecommon reference numerals, and their detailed description will beomitted.

In the DRAM of this embodiment, a start signal generator 82 is formed inreplace of the release detecting circuit 72 and the level detectingcircuit 74 described in the forth embodiment. The other configuration isidentical to that in FIG. 3 (the first embodiment).

The start signal generator 82 are constructed of a CMOS inverter 82 afor receiving a CE2X signal (internal signal) which is an inverted CE2signal, a MOS capacitor 82 b connected with the output of the CMOSinverter 82 a, and a differential amplifier 82 c for receiving the inputof the CMOS inverter 82 a and the reference voltage VREF. Thedifferential amplifier 82 c comprising a current mirror circuit, turns astart signal STTPZ to high level when the voltage of a node ND4 is lowerthan the reference voltage VREF.

The pMOS of the CMOS inverter 82 a has a long channel length to havehigh on-resistance. A CR time constant circuit is constructed of thepMOS of the CMOS inverter 82 a and the MOS capacitor 82 b. Utilizing theon-resistance of a transistor to construct the CR time constant circuitallows the layout to be reduced in size than the case of utilizingdiffused resistance.

FIG. 21 shows the operation timings of the above-described DRAM at thetime of entry to and exit from the low power consumption mode. Firstly,when the CE2 signal (not shown) is turned to low level, the CE2X signalis turned to high level and the DRAM enters the low power consumptionmode. A generator for the internal power supply voltage VII and agenerator for the boost voltage VPP terminate their operation. The CMOSinverter 82 a in FIG. 20 upon receiving the high level of the CE2Xsignal, turns the nMOS on and a node ND4 to low level (FIG. 21( a)). Thedifferential amplifier 82 c turns a STTPZ signal to high level when thevoltage of the node ND4 is lower than the reference voltage VREF (FIG.21( b)).

Subsequently, the CE2 signal being turned to high level and the CE2Xsignal to low level, the DRAM is released from the low power consumptionmode (FIG. 21( c)). The CMOS inverter 82 in FIG. 20 upon receiving thelow level of the CE2X signal, turns the pMOS on and the node ND4 to highlevel (FIG. 21( d)). At this time the voltage of the node ND4 graduallyrises in accordance with the time constant determined by theon-resistance of the pMOS and the CMOS capacitor. The differentialamplifier 82 c turns the STTPZ signal to low level when the voltage ofthe node ND4 is higher than the reference voltage VREF (FIG. 21( e)).

Consequently, the STTPZ signal (reset signal) is activated (high level)and the internal circuit is initialized during a period T2 from the exitfrom the low power consumption mode. The period T2 is set after the exitfrom the low power consumption mode in correspondence with a periodwhere the internal power supply voltage VII is lower than apredetermined voltage so that the operation of the internal circuitsupplied with the internal power supply voltage VII can not be ensured.In other words, the start signal generator 82 operates as a timer fordetermining the length of the period T2.

This embodiment can also achieve effects similar to those of theforegoing fourth embodiment. In this embodiment, moreover, at the timeof the exit from the low power consumption mode the start signalgenerator 82 is operated as a timer to generate the STTPZ signal and theinternal circuit is initialized during the period T2 after the exit fromthe low power consumption mode. This makes it possible to reliably resetthe internal circuit and prevent the malfunction of the internal circuitwhen the low power consumption mode shifts to the normal operating mode.

Since the start signal generator 82 is operated as a CR time constantcircuit, it is possible to set the period T2 based on the propagationdelay time of a signal propagated to the CR time constant circuit. Thismakes it possible to set a period necessary for resetting the internalcircuit by a simple circuit.

The on-resistance of the pMOS is utilized to form the CR time constantcircuit so that the layout of the start signal generator 82 can bereduced in size.

FIG. 22 shows a seventh embodiment of a semiconductor memory device anda method of controlling the same in the present invention. Here, thesame circuits as those described in the first embodiment will not bedescribed in detail by designating them by the common referencenumerals.

In this embodiment, the DRAM includes the VII starter 10, the VDDstarter 12, a low power entry circuit 84, the command decoder 16, aninternal voltage generator 86 and a main circuit unit 88. The internalvoltage generator 86 has the low-pass filter 22, the reference voltagegenerator 24, a VPP detector 90, a booster 92, a precharging voltagegenerator 94, an internal supply voltage generator 96, a VBB detector 98and a substrate voltage generator 100. The main circuit unit 88 has thememory core 38, the peripheral circuit 40, a frequency divider 102 andan oscillator 104. These frequency divider 102 and oscillator 104 arecontrol circuits for generating timing signals to execute the refreshoperations automatically in the self-refresh mode.

FIG. 23 shows the detail of the reference voltage generator 24.

The reference voltage generator 24 is provided with a reference voltagegenerator 24 a for generating a reference voltage VREF, a starter 24 bconsisting of pMOS, a differential amplifier 24 c, and a regulator 24 d.

The reference voltage generator 24 a has a current mirror circuit madeof a pMOS, two nMOSes connected individually in series with the currentmirror circuit, and a register connected between the source of one ofthe nMOSes and the ground line VSS. The output of the reference voltagegenerator 24 a is connected with the gate of one nMOS and the drain ofthe other nMOS, from which the reference voltage VREF is generated. Thegate of the other nMOS is connected with the source of the one nMOS.

The starter 24 b raises the reference voltage VREF to the high levelwhile the start signal STTCRX is activated after the power-on.

The differential amplifier 24 c has a current mirror part made ofpMOSes, a differential input part made of nMOSes and an nMOS supplyingthe gate with reference voltage and connecting the differential inputpart with the ground line VSS. The one nMOS of the differential inputpart is supplied at its gate with the reference voltage VREF, and theother nMOS is supplied at its gate with the reference voltage VRFV.

The regulator 24 d is constructed by connecting a pMOS and fiveresistors in series between the power supply line VDD and the groundline VSS. From the connection nodes of the individual elements, thereare individually outputted reference voltages VRFV, VPREF, VPRREFL andVPRREFH. With the two terminals of the resistor connected with theground line VSS, there are connected the source and drain of the nMOSwhich is controlled by a low power signal NAPX. The resistor, asconnected with the ground line VSS, is bypassed when the low powersignal NAPX is activated (to a low level). During the low powerconsumption mode, therefore, the levels (absolute values) of thereference voltages VRFV, VPREF, VPRREFL, and VPRREFH vary, therebylowering the voltages, compared with the normal operation mode.

FIG. 24 shows the detail of the internal supply voltage generator 96.

This internal supply voltage generator 96 is constructed by eliminatingthe switch circuit 32 e and the nMOS 32 d from the VII internal supplyvoltage generator 32 of the first embodiment shown in FIG. 5 and byadding a stabilized capacitor 96 a, a switch 96 b, and an nMOS 96 c. Thestabilized capacitor 96 a stores a portion of the electric chargesupplied to the internal power supply line VII to reduce the shift ofthe power supply voltage VII, as might otherwise be caused by the powersupply noise. The switch 96 b is formed of a CMOS transmission gate, forexample. The nMOS 96 c, as arranged between the internal power supplyline VII and the ground line VSS, is supplied at its gate with theinverted logic of the low power signal NAPX through an inverter.

The switch 96 b is turned off, when the low power signal NAPX isactivated, to disconnect the regulator 32 c and the internal circuit. Atthis time, the nMOS 96 c is turned off so that the internal power supplyline VII drops to the ground voltage (0 V). The power supply voltage VIIis not supplied to the internal circuit so that the leakage current ofthe transistor or the like in the internal circuit does not occur duringthe power consumption mode. Specifically, the power consumption of theinternal circuit can be lowered to zero. At this time, the connectionbetween the regulator 32 c and the stabilized capacitor 96 a is kept sothat the stabilized capacitor 96 a stores the electric charge as in thenormal operation.

After the low consumption mode is released, the switch 96 b is turned onwhen the low power signal NAPX is inactivated. Simultaneously with this,the nMOS 96 c is turned off to connect the regulator 32 c and theinternal circuit. At this time, not only the electric charge suppliedfrom the regulator 32 c but also the electric charge stored in thestabilized capacitor 96 a is supplied to the internal power supply lineVII so that this internal power supply voltage VII is raised andsupplied to the internal circuit. As a result, this internal circuit canbe operated immediately after the low power consumption mode isreleased.

FIG. 25 shows the booster 92, the VPP detector 90, the substrate voltagedetector 100 and the VBB detector 98.

The booster 92 is provided with an oscillator 106 to be operated when aboost enable signal VPPEN is activated, and a plurality of units 108 and110. The unit 108 receives pulse signals PLS1-PLS6 from the oscillator106 to generate the boost voltage VPP when the low power signal NAPX isactivated. The unit 110 generates the boost voltage VPP at all times inresponse to the pulse signals PLS1-PLS6 from the oscillator 106,irrespective of the low power signal NAPX. On the basis of theactivation of the low power signal NAPX, the unit 108 stops itsoperation so that the power consumption of the booster 92 is loweredduring the power consumption mode. In this low power consumption mode,the refreshing operation is not executed so that no problem arises evenif the drivability of the booster 92 drops, as will be describedhereinafter. The number of the units 110 to be operated at all timesirrespective of the operation mode is determined according to the timeperiod (i.e., the timing specification) till the normal operation or therefreshing operation is executed after the return from the low powerconsumption mode.

The substrate voltage generator 100 is provided with a plurality ofunits 112 to be operated by activating a substrate voltage detectionsignal VBBDET and inactivating the low power signal NAPX, and aplurality of units 114 to be operated by activating the substratevoltage detection signal VBBDET. When the operations of the units 112are stopped on the basis of the activation of the low power signal NAPX,the power consumption of the substrate voltage generator 100 dropsduring the power consumption mode. The number of the units 114 to beoperated at all times irrespective of the operation mode is determinedaccording to the time period (i.e., the timing specification) after thereturn from the low power consumption mode to the execution of thenormal operation or the refreshing operation.

FIG. 26 shows the detail of the unit 108 of the booster 92.

This unit 108 has four capacitors 108 a, 108 b, 108 c and 108 d eachmade of an nMOS, and pMOSes 108 e and 108 f to operate as switches. Thecapacitors 108 a, 108 b, 108 c and 108 d receive the inverted logics ofpulse signals PLS1, PLS2, PLS3 and PLS4, respectively, at their one-sideterminals when the low power signal NAPX is inactivated. The otherterminals of the capacitors 108 a-108 d are connected with the powersupply line VDD through a plurality of diode-connected nMOSes. The gatesof the pMOSes 108 e and 108 f receive pulse signals PLS5 and PLS6,respectively, at their gates through the logic gates when the low powersignal NAPPX is inactivated.

The pulse signals PLS1, PLS2 and PLS5 and the pulse signals PLS3, PLS4and PLS6 are in opposite phases to each other. The high-level voltagesof the low power signal NAPX and the pulse signals PLS5 and PLS6 are soequalized to the boost voltage VPP as to turn off the pMOSes 108 e and108 f reliably.

The capacitors 108 a and 108 b, and 108 c and 108 d are alternatelycharged and discharged in response to the pulse signals PLS1, PLS2, PLS3and PLS4 inputted. The pMOSes 108 e and 108 f are alternately turned onin synchronization with the pumping operations of the capacitors 108 aand 108 b, and the capacitors 108 c and 108 d. By these pumpingoperations, moreover, the power supply voltage VDD is boosted to theboost voltage VPP. The unit 108 stops its operation when the low powersignal NAPX is activated.

FIG. 27 shows the detail of the unit 110 of the booster 92.

This unit 110 is a circuit which is made by eliminating the logics ofthe low power signals NAPX and NAPPX from the unit 108. In other words,the unit 110 operates at all times after the power supply on to generatethe boost voltage VPP.

FIG. 28 shows the detail of the VPP detector 90.

This VPP detector 90 is provided with a differential amplifier 90 a anda voltage generator 90 b for supplying its voltage to one input of thedifferential amplifier 90 a.

This differential amplifier 90 a has a current mirror part 90 c composedof pMOSes, and a pair of differential input parts 90 d and 90 e composedof nMOSes. Both the inputs of the differential input parts 90 d and 90 ereceive the reference voltage VPREF and a control voltage VPP2 which isgenerated by shifting the level of the boost voltage VPP from thevoltage generator 90 b. The differential input part 90 d is connectedwith the ground line VSS through the nMOS which is always on, and thedifferential input part 90 e is connected with the ground line VSSthrough the nMOS which is turned on when the low power signal NAPX isinactivated.

In short, the differential input part 90 d operates at all times, andthe differential input part 90 e operates only when the low power signalNAPX is inactivated. During the low power consumption mode, thedifferential input part 90 e stops its operation so that the powerconsumption is reduced. The differential amplifier 90 a activates theboost enable signal (to the high level) when the control voltage VPP2 islower than the reference voltage VPREF.

The voltage generator 90 b is constructed by connecting three resistorsin series between the node for generating the boost voltage VPP and theground line VSS. The control voltage VPP2 is outputted from the otherterminal of the resistor on the side of the node for supplying the boostvoltage VPP. With the two terminals of the resistor connected with theground line VSS, there are individually connected the source and thedrain of the nMOS which is controlled with the low power signal NAPX.The resistor connected with the ground line VSS is bypassed when the lowpower signal NAPX is activated. During the low power consumption mode,therefore, the level of the control voltage VPP2 drops.

FIG. 29 shows the detail of the unit 112 of the substrate voltagegenerator 100.

This unit 112 is provided with an oscillator 112 a and a pumping circuit112 b.

The oscillator 112 a is constructed as a ring oscillator composed of oddstages of logic gates. The oscillator 112 a operates when the substratevoltage detection signal VBBDET is activated but when the low powersignal NAPX is inactivated.

The pumping circuit 112 b includes a voltage supplying part 112 c havingthree pMOSes and one nMOS connected in series between the power supplyline VDD and the pumping node PND, a capacitor 112 d composed of a pMOSconnected at its gate with the pumping node PND, an nMOS 112 e forconnecting the pumping node PND and the ground line VSS when the pumpingnode PND is at the high level, and a diode-connected nMOS 112 f forconnecting the pumping node PND and the substrate node VBB.

In the pumping circuit 112 b, the pumping node PND interchangeably hasthe ground voltage and a negative voltage when the pMOSes and nMOS ofthe voltage supplying part 112 c and the capacitor 112 d receive theclock signal from the oscillator 112 a. When the pumping node PND has anegative voltage, moreover, the electric charge of the substrate nodeVBB is pumped out to set the substrate node VBB to a negative voltage.The unit 112 stops its operation during the power consumption mode(while the low power signal NAPX is active).

FIG. 30 shows the detail of the unit 114 of the substrate voltagegenerator 100.

This unit 114 is provided with an oscillator 114 a and a pumping circuit114 b.

The oscillator 114 a is a circuit which is made by eliminating the logicof the low power signal NAPX from the oscillator 112 a of the unit 112.In short, the oscillator 114 a operates in response to the substratevoltage detection signal VBBDET even during the power consumption modeto generate the substrate voltage VBB. The pumping circuit 114 b is acircuit identical to the pumping circuit 112 b of the unit 112.

FIG. 31 shows the detail of the VBB detector 98.

This VBB detector 98 is provided with two detection units 98 a and 98 b,and an OR circuit 98 c for outputting the OR logic of the detectionresults of those units 98 a and 98 b as the substrate voltage detectionsignal VBBDET.

The detection unit 98 a includes: a reference voltage generating part 98d having a resistor; a pMOS and a resistor connected in series betweenthe internal power supply line VII and the ground line VSS; a leveldetecting part 98 e having two nMOSes connected in series; a CMOSinverter 98 f having a pMOS connected with the power supply line VIIthrough a pMOS load circuit; and an nMOS 98 g for connecting the outputnode NOUT1 of the level detecting part 98 f with the ground line VSS.The gate of the pMOS of the reference voltage generating part 98 d andthe gate of the nMOS 98 g receive the low power signal NAPX. Therefore,the detection unit 98 a is inactivated in the normal operation mode butis activated during the power consumption mode. The voltage of theoutput node NOUT1 of the level detecting part 98 e rises, whenactivated, with the rise of the substrate voltage VBB. In thisembodiment, the CMOS inverter 98 f outputs the low level in response tothe detection result (i.e., the voltage of the output node NOUT1) at thelevel detecting part 98 d when the substrate voltage VBB is boosted to−0.5 V. The OR circuit 98 c activates the substrate voltage detectionsignal VBBDET when it receives the low level from the CMOS inverter 98f.

In the detection unit 98 b, the gate of the pMOS of the referencevoltage generating part 98 d and the gate of the nMOS 98 g are suppliedwith the inverted logic of the low power signal NAPX. The remainingconstructions are identical to those of the detection unit 98 a. In thisembodiment, the CMOS inverter 98 f outputs the low level in response tothe detection result at the level detecting part 98 e (i.e., the voltageof the output node NOUT1) when the substrate voltage VBB rises to −1.0 Vin the normal operation mode. The output of the reference voltagegenerating part 98 d of the detection unit 98 b has the ground voltageVSS (at 0 V) when the low power signal NAPX is at the low level (duringthe power consumption mode). Therefore, the output node NOUT2 of thelevel detecting part 98 e has the low level at all times. In short, thedetection unit 98 b is inactivated during the power consumption mode.

Therefore, the VBB detector 98 uses only the detection unit 98 b in thenormal operation mode and activates the substrate voltage detectionsignal VBBDET when the substrate voltage VBB rises to −1.0 V. When thesubstrate voltage detection signal VBBDET is activated, the units 112and 114 of the substrate voltage generating circuit 100, as shown inFIGS. 29 and 30, operate so that the substrate voltage VBB drops.

During the low power consumption mode, on the other hand, the VBBdetector 98 activates the detection unit 98 a but inactivates thedetection unit 98 b when the low power signal NAPX is activated. As aresult, the power consumption of the VBB detector 98 is reduced. Thelevel of the substrate voltage VBB is detected during the powerconsumption mode only by the detection unit 98 a so that the substratevoltage detection signal VBBDET is activated when the substrate voltageVBB rises to −0.5 V. The detection level (in an absolute value) of thesubstrate voltage VBB becomes low so that the absolute value of thesubstrate voltage VBB to be generated by the substrate voltage generator100 is reduced. In other words, the operation of the substrate voltagegenerator 100 is further suppressed during the power consumption modethan during the normal operation mode. As a result, the powerconsumption can be reduced. The difference between the substrate voltageVBB and the ground voltage VSS is decreased, thereby reducing thesubstrate leakage. Therefore, the occurrence frequency of the substratevoltage detection signal VBBDET is lowered to decrease the operationfrequency of the substrate voltage generator 100. As a result, the powerconsumption can be further reduced.

FIG. 32 shows the detail of the precharging voltage generator 94.

This precharging voltage generator 94 is provided with differentialamplifiers 94 a and 94 b and a VPR generator 94 c.

The differential amplifier 94 a has a current mirror part 94 d composedof pMOSes, and a pair of differential input parts 94 e and 94 f composedof nMOSes. Both the inputs of the differential input parts 94 e and 94 freceive the reference voltage VPRREFL and the precharging voltage VPR.The differential input part 94 e is connected with the ground line VSSthrough the always on nMOS, and the differential input part 94 f isconnected with the ground line VSS through the nMOS which is turned onwhen the low power signal NAPX is inactivated.

In short, the differential input part 94 e operates at all times, butthe differential input part 94 f operates only when the low power signalNAPX is inactivated. The differential input part 94 f stops itsoperation during the power consumption mode so that the powerconsumption is reduced. The differential amplifier 94 a sets the outputnode NOUT3 to the low level when the reference voltage VPRREFL is higherthan the precharging voltage VPR.

The differential amplifier 94 b has a current mirror part 94 g composedof nMOSes, and a pair of differential input parts 94 h and 94 i composedof pMOSes. Both the inputs of the differential input parts 94 h and 94 ireceive the reference voltage VPRREFH and the precharging voltage VPR.The differential input part 94 g is connected with the power supply lineVDD through the always on pMOS, and the differential input part 94 i isconnected with the power supply line VDD through the pMOS which isturned on when the low power signal NAPX is inactivated.

The differential input part 94 h operates at all times, but thedifferential input part 94 i operates only when the low power signalNAPX is inactivated. During the low power consumption mode, thedifferential input part 94 i stops its operation so that the powerconsumption is reduced. The differential amplifier 94 b sets the outputnode NOUT4 to the low level when the reference voltage VPRREFH is lowerthan the precharging voltage VPR.

The VPR generator 94 c has a pMOS and an nMOS connected in seriesbetween the power supply line VDD and the ground line VSS. The gate ofthe pMOS connects the output node NOUT3. The gate of the nMOS connectsthe output node NOUT4. From the drains of the pMOS and the nMOS, thereis outputted the precharging voltage VPR. This precharging voltage VPRis used as the equalizing voltage of the paired bit lines and the platevoltage of the memory cells in the memory core 38.

The inactivation of the differential input parts 94 f and 94 i duringthe power consumption mode deteriorates the response of the prechargingvoltage generator 94 to a shift in the precharging voltage. As will bedescribed hereinafter, however, the reading operation and the refreshingoperation are not executed during the power consumption mode so that noproblem arises even if the response of the precharging voltage generator94 is lowered.

FIG. 33 shows the detail of the oscillator 104.

This oscillator 104 is provided with a ring oscillator 104 a having oddstages of CMOS inverters connected in cascade, and a buffer 104 b forextracting an oscillating signal OSCZ from the ring oscillator 104 a.Frames of broken lines in FIG. 33 are switches for adjusting the stagenumber (corresponding to the self-refreshing period) of the ringoscillator 104 a. The on/off of these switches are set by the blow ofthe polysilicon fuse or by the layout pattern of the photomask of thewiring layer. In this example, the stage number of the ring oscillator104 a is set to “7”. The sources of the pMOSes and the nMOSes of theCMOS inverters are connected with the internal power supply line VII andthe ground line VSS, respectively, through the pMOS loads and the nMOSloads. The gates of the pMOS loads and the nMOS loads are controlledwith the control voltages PCNTL and NCNTL, respectively. The oscillator104 has pMOSes and nMOSes for receiving the control of the low powersignal NAPX. When the low power signal NAPX is activated, those pMOSesare turned on to fix the predetermined node of the ring oscillator 104 ato the high level, but the connections between the nMOSes of the CMOSinverters and the ground line VSS are broken when those nMOSes areturned off. As a result, the oscillator 104 stops its operation duringthe power consumption mode.

FIG. 34 shows a generator 116 formed in the oscillator 104 forgenerating the control voltages PCNTL and NCNTL.

This generator 116 is provided with: a pMOS, a pMOS diode and a resistorconnected in series between the internal power supply line VII and theground line VSS; a resistor, an nMOS diode and an nMOS connected inseries between the internal power supply line VII and the ground lineVSS; a MOS capacitor arranged between a node for generating the controlvoltage PCNTL and the internal power supply line VII; and a MOScapacitor arranged between a node for generating the control voltageNCNTL and the ground line VSS.

The control voltage PCNTL is generated from the connection node betweenthe pMOS diode and the resistor, and varies with the shift of theinternal power supply voltage VII. The control voltage NCNTL isgenerated from the connection node between the nMOS diode and theresistor, and varies with the shift of the ground voltage VSS.Therefore, the gate-to-source voltage of the pMOS and the nMOS of theCMOS inverter shown in FIG. 33 is always constant so that theoscillation period of the ring oscillator 104 a is constant irrespectiveof the shift of the internal power supply voltage VII. The MOS capacitorprevents the high-frequency noises to occur on the internal power supplyline VII and the ground line VSS from influencing the control voltagePCNTL and the control voltage NCNTL. As a result, the shifts of theinternal power supply voltage VII and the ground voltage VSS arecanceled so that the oscillating signal OSCZ is generated always for apredetermined period while the oscillating circuit 104 is active (in theself-refreshing mode).

The pMOS and the nMOS are turned off when the low power signal NAPX isactive. In other words, the generator 116 is inactivated during thepower consumption mode. At this time, the control voltages PCNTL andNCNTL turns to the low level and the high level, respectively.

In the DRAM thus far described, like the first embodiment, the low powerentry circuit 84 shown in FIG. 22 activates the low power signal NAPX(to the low level) to enter the chip to the low power consumption modewhen it receives the chip enable signal CE2 at the low level from theexterior.

When the low power signal NAPX is activated, the reference voltagegenerator 24 shown in FIG. 23 lowers the levels of the referencevoltages VRFV, VPREF, VPREFL and VPREFH. The VPP detector 90 shown inFIG. 28 inactivates the differential input part 90 e and simultaneouslylowers the level of the control voltage VPP2 to be supplied to thedifferential input part 90 d. The unit 108 of the booster 92, as shownin FIG. 25, and the unit 112 of the substrate voltage generator 100 stoptheir operations. The VBB detector 98 shown in FIG. 31 inactivates thedetection unit 98 b but activates the detection unit 98 a to raise thedetection level of the substrate voltage VBB. Specifically, thesubstrate voltage detection signal VBBDET is activated when thesubstrate voltage VBB rises to −0.5 V. The differential amplifiers 94 aand 94 b of the precharging voltage generator 94 shown in FIG. 32inactivate the differential input parts 94 f and 94 i, respectively. Theoscillator 104 shown in FIG. 33 stops its operation. The generator 116shown in FIG. 34 is inactivated.

FIG. 35 shows the operations of the oscillator 104 and the frequencydivider 102.

When the low power signal NAPX is activated, the oscillator 104 sets theoscillating signal OSCZ to the low level. Since the oscillating signalOSCZ stops its oscillation, the frequency division by the frequencydivider 102 stops so that the self-refreshing timer signal SRTZ turns tothe low level. Therefore, the power consumption of the frequency divider102 is substantially zero.

Thus, the plurality of control circuits suspends their operations orlower detection capability of signal level, thereby substantiallyreducing the power consumption during the low power consumption mode,compared to the conventional art. Some of the control circuits continuetheir operations in the low detection state so that the normal operationcan be started immediately after the release from the low powerconsumption mode.

In this embodiment, the oscillator 104 for self-refresh is stoppedduring the power consumption mode to stop operations performed in theself-refreshing mode, as has been described above. As a result, thepower consumption during the power consumption mode can be reduced.

Since the refreshing operation is not executed, the internal voltagegenerator 86 may be operated with a power enough to compensate theelectric power (the leakage current) to be consumed by the peripheralcircuit 40. As a result, the power consumption during the powerconsumption mode can be reduced.

The internal voltages VPP, VBB and VPR are supplied to the internalcircuit (including the peripheral circuit 40, the memory core 38, andthe like) even during the power consumption mode. Therefore, theperipheral circuit 40, the memory core 38, and the like can be operatedjust after the release from the low power consumption mode.

During the low power consumption mode, the operations of the unit 108 ofthe booster 92 and the unit 112 of the substrate voltage generator 100are stopped so that the power consumption during the power consumptionmode can be further reduced.

During the low power consumption mode, the connection between theinternal power supply line VII and the stabilized capacitor 96 a iskept, and the connection between the internal power supply line VII andthe internal circuit (the peripheral circuit 40 and the memory core 38)is broken. The power supply to the peripheral circuit 40 is stopped sothat the leakage current to the peripheral circuit 40 can disappear toreduce the power consumption to zero. When the internal power supplyline VII and the internal circuit are connected after the release fromthe low power consumption mode, the voltage corresponding to theelectric charge stored in the stabilized capacitor 96 a is supplied tothe internal circuit through the internal power supply line VII. Beforethe internal supply voltage generator 96 generates a predeterminedinternal power supply voltage VII after the release from the low powerconsumption mode, therefore, the voltage corresponding to the electriccharge stored in the stabilized capacitor 96 a can be applied to theinternal circuit. As a result, the internal circuit can operateimmediately after the release from the low power consumption mode.

During the low power consumption mode, the differential input part 90 ein the differential amplifier 90 a of the VPP detector 90 and thedifferential input parts 94 f and 94 i in the differential amplifiers 94a and 94 b of the precharging voltage generator 94 are inactivated sothat the power consumption of the differential amplifiers 90 a, 94 a,and 94 b can be reduced.

During the low power consumption mode, the operations of the unit 108 ofthe booster 92 and the unit 112 of the substrate voltage generator 100are stopped, so that the transient dispersions of the boost voltage VPPand the substrate voltage VBB are suppressed. In other words, thedifference between the maximum and the minimum of the boost voltage VPPand the substrate voltage VBB can be decreased to reduce the leakagecurrent.

By lowering the levels of the reference voltages VPREF, VRFV (VII),VPRREFH and VPRREFL to be generated by the reference voltage generator24, the absolute values of the detection levels of the VPP detector 90,the VBB detector 98 and the precharging voltage generator 94 arereduced, and the levels (in absolute values) of the boost voltage VPP,the substrate voltage VBB and the precharging voltage VPR to begenerated by the precharging voltage generator 94 are reduced. Since thevoltages are lowered, the leakage current can be reduced to lower thepower consumption.

In the embodiment described above, the present invention is applied tothe DRAM. However, the present invention is not limited to thisembodiment. For example, the present invention may be applied to asemiconductor memory such as SDRAMs (Synchronous DRAMs), DDR SDRAMs(Double Data Rate SDRAMs), or FCRAMs (Fast Cycle RAMs).

A semiconductor fabrication process to which the present invention isapplied is not restricted to the CMOS process, but it may well be aBi-CMOS process.

The foregoing second embodiment has been described on an example inwhich the low power entry circuit 50 is formed by connecting theplurality of delay circuits 54 c in series. However, the presentinvention should not be limited thereto but may form the low power entrycircuit by using a latch circuit to be controlled by the STTCRX signal,for example. In this modification, the circuit scale is reduced.

The foregoing third embodiment has been described on the example usingthe dedicated low power consumption mode signal /LP. This DRAM can besupplied even to the user requiring no low power consumption mode, forexample, by pulling up the /LP signal on the chip and providing noterminal for the /LP signal. This /LP signal may be connected with thepower supply voltage VDD by bonding or blowing the fuse. Alternatively,the /LP signal may be connected with the power supply voltage VDD byselecting photo masks of a wiring layer.

The foregoing fifth embodiment has been described on an example of thecomparison between the boost voltage VPP and the power supply voltageVDD. However, the present invention is not limited to this embodiment,for example, the boost voltage VPP may well be compared with thereference voltage VREF which is generated by stepping down the powersupply voltage VDD.

The foregoing sixth embodiment has been described on an example ofoperating the start signal generator 82 as a timer for determining thelength of the period T2 at the exit from the low power consumption modeand activating a STTPZ signal (reset signal) for initializing aninternal circuit during the period T2. The present invention is notlimited to this embodiment. For example, at the time of the exit fromthe low power consumption mode, a counter operating in normal operationis operated as a timer so as to count a predetermined number. The resetsignal for initializing an internal circuit may well be activated duringa period where the counter counts the number. A refresh counterindicating the refresh address of memory cells or the like can be usedas the counter.

The invention is not limited to the above embodiments and variousmodifications may be made without departing from the spirit and thescope of the invention. Any improvement may be made in part or all ofthe components.

1-6. (canceled)
 7. A method of operating a dynamic random access memoryincluding dynamic memory cells in a memory system, comprising:outputting a first command to the dynamic random access memory through amemory bus to put the dynamic random access memory in a low powerconsumption mode by a CPU, the first command including a firstcombination of a plurality of control signals, in which the dynamicmemory cells in the dynamic random access memory do not retain data inthe low power consumption mode; outputting a second command to thedynamic random access memory through the memory bus to put the dynamicrandom access memory out of the low power consumption mode by the CPU,the second command including a second combination of the plurality ofcontrol signals; and waiting for completion of initialization of thedynamic random access memory during a first period, the initializationbeing performed in response to the second command, wherein the dynamicrandom access memory continues to be supplied with a power supplyvoltage in the low power consumption mode.
 8. The method of operatingthe dynamic random access memory including dynamic memory cells in amemory system according to claim 7, wherein the CPU controls anon-volatile memory including flash memory cells through the memory bus.9. The method of operating the dynamic random access memory includingdynamic memory cells in a memory system according to claim 7, furthercomprising keeping at least one signal of the plurality of controlsignals to a first voltage to maintain the low power consumption modeafter the outputting the first command.
 10. The method of operating thedynamic random access memory including dynamic memory cells in a memorysystem according to claim 7, further comprising stopping an operation ofan internal voltage generator of the dynamic random access memoryconfigured to supply an internal voltage to the dynamic memory cells inthe low power consumption mode.
 11. The method of operating the dynamicrandom access memory including dynamic memory cells in a memory systemaccording to claim 7, further comprising stopping a supply of aninternal voltage to the dynamic memory cells in the low powerconsumption mode.
 12. The method of operating the dynamic random accessmemory including dynamic memory cells in a memory system according toclaim 7, further comprising supplying an internal voltage to the dynamicmemory cells in response to the second command, in which the internalvoltage is stabilized by the initialization.
 13. The method of operatingthe dynamic random access memory including dynamic memory cells in amemory system according to claim 7, wherein the first period is equal toor more than 200 micro seconds.
 14. A method of operating a dynamicrandom access memory including dynamic memory cells in a memory system,comprising: outputting a first command to the dynamic random accessmemory through a memory bus to put the dynamic random access memory in alow power consumption mode by a CPU, the first command including a firstcombination of a plurality of control signals, in which the dynamicmemory cells in the dynamic random access memory do not retain datatherein by stopping an operation of an internal voltage generatorconfigured to supply an internal voltage to the dynamic memory cells inthe low power consumption mode; and outputting a second command to thedynamic random access memory through the memory bus to put the dynamicrandom access memory out of the low power consumption mode by the CPU,the second command including a second combination of the plurality ofcontrol signals, wherein the dynamic random access memory continues tobe supplied with a power supply voltage in the low power consumptionmode.
 15. The method of operating the dynamic random access memoryincluding dynamic memory cells in a memory system according to claim 14,wherein the CPU controls a non-volatile memory including flash memorycells through the memory bus.
 16. The method of operating the dynamicrandom access memory including dynamic memory cells in a memory systemaccording to claim 14, further comprising keeping at least one signal ofthe plurality of control signals to a first voltage to maintain the lowpower consumption mode after the outputting the first command.
 17. Themethod of operating the dynamic random access memory including dynamicmemory cells in a memory system according to claim 14, furthercomprising waiting for completion of initialization of the dynamicrandom access memory during a first period after the outputting thesecond command, the initialization being performed in response to thesecond command.
 18. The method of operating the dynamic random accessmemory including dynamic memory cells in a memory system according toclaim 17, wherein the internal voltage supplied to the dynamic memorycells in response to the second command is stabilized by theinitialization.
 19. The method of operating the dynamic random accessmemory including dynamic memory cells in a memory system according toclaim 17, wherein the first period is equal to or more than 200 microseconds.
 20. A method of operating a dynamic random access memoryincluding dynamic memory cells in a memory system, comprising:outputting a first command to the dynamic random access memory through amemory bus to put the dynamic random access memory in a low powerconsumption mode by a CPU, the first command including a firstcombination of a plurality of control signals, in which the dynamicmemory cells in the dynamic random access memory do not retain datatherein by stopping a supply of an internal voltage in the low powerconsumption mode; and outputting a second command to the dynamic randomaccess memory through the memory bus to put the dynamic random accessmemory out of the low power consumption mode by the CPU, the secondcommand including a second combination of the plurality of controlsignals, wherein the dynamic random access memory continues to besupplied with a power supply voltage in the low power consumption mode.21. The method of operating the dynamic random access memory includingdynamic memory cells in a memory system according to claim 20, whereinthe CPU controls a non-volatile memory including flash memory cellsthrough the memory bus.
 22. The method of operating the dynamic randomaccess memory including dynamic memory cells in a memory systemaccording to claim 20, further comprising keeping at least one signal ofthe plurality of control signals to a first voltage to maintain the lowpower consumption mode after the outputting the first command.
 23. Themethod of operating the dynamic random access memory including dynamicmemory cells in a memory system according to claim 20, furthercomprising waiting for completion of initialization of the dynamicrandom access memory during a first period after the outputting thesecond command, the initialization being performed in response to thesecond command.
 24. The method of operating the dynamic random accessmemory including dynamic memory cells in a memory system according toclaim 23, wherein the internal voltage supplied to the dynamic memorycells in response to the second command is stabilized by theinitialization.
 25. The method of operating the dynamic random accessmemory including dynamic memory cells in a memory system according toclaim 23, wherein the first period is equal to or more than 200 microseconds.